求助关于vhdl的问题，具体原程序如下~求解决方法~

Question

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADCINT ISPORT(D :IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK : IN STD_LOGIC;EOC : IN STD_LOGIC;ALE : OUT STD_LOGIC;START : OUT STD_LOGIC;OE : OUT STD_LOGIC;ADDA : OUT STD_LOGIC;LOCK0 : OUT STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ADCINT;ARCHITECTURE BEHAV OF ADCINT ISTYPE STATES IS (STO,ST1,ST2,ST3,ST4,);SIGNAL current_state,next_state:states :=st0;SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL LOCK :STD_LOGIC;BEGINADDA<='1';Q<=REGL; LOCK0<=LOCK;COM: PROCESS(CURRENT_STATE,EOC) BEGIN CASE CURRENT_STATE ISWHEN ST0=>ALE<='0';START<='0';LOCK<='0';OE<='0'; NEXT_ATATE <=ST1;WHEN ST1=>ALE<='1';START<='1';LOCK<='0';OE<='0'; NEXT_ATATE <=ST2;WHEN ST2=>ALE<='0';START<='0';LOCK<='0';OE<='0';IF (EOC='1') THEN NEXT_STATE<=ST3;ELSE NEXT_STATE<=ST2;END IF;WHEN ST3=>ALE<='0';START<='0';LOCK<='0';OE<='1';NEXT_STATE<=ST4;WHEN ST4=>ALE<='0';START<='0';LOCK<='0';OE<='1';NEXT_STATE<=ST0;WHEN OTHERS=>NEXT_STATE<=ST0;END CASE;END PROCESS COM;REG PRECESS (CLK)BEGINIF (CLK'ENENT AND CLK='1') THEN CURRENT_STATE<NEXT_STATE;ENDIF;END PROCESS REG;LATCH1:PROCESS (LOCK)BEGINIF LOCK='1' AND LOCK'EVENT THEN REGL<=D;END IF;END PROCESS LATCH1;END BEHAV;Error (10500): VHDL syntax error at mylunwen.vhd(13) near text "END"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"Error (10500): VHDL syntax error at mylunwen.vhd(15) near text ")"; expecting an identifierError (10500): VHDL syntax error at mylunwen.vhd(19) near text "BEGIN"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"

Answer 1

你这个程序有些不规范，比如SIGNAL current_state,next_state:states :=st0;
这里是小写，而你在后面又用大写，建议前后大小写保持一致；还有就是有些是在输入的时候把一些字母输错了，自己以后写程序要注意；一定还要注意一些标点符号，比如“）”，“；”之类的。还有END IF,END与IF之间一定要有一个空格。我把改好之后的程序写在下面，你自己对照看一下。
修改后的程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
PORT(D :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK : IN STD_LOGIC;
EOC : IN STD_LOGIC;
ALE : OUT STD_LOGIC;
START : OUT STD_LOGIC;
OE : OUT STD_LOGIC;
ADDA : OUT STD_LOGIC;
LOCK0 : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ADCINT;
ARCHITECTURE BEHAV OF ADCINT IS
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4);
SIGNAL CURRENT_STATE,NEXT_STATE:STATES :=ST0;
SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK :STD_LOGIC;
BEGIN
ADDA<='1';
Q<=REGL;
LOCK0<=LOCK;
COM: PROCESS(CURRENT_STATE,EOC)
BEGIN
CASE CURRENT_STATE IS
WHEN ST0=>ALE<='0';START<='0';LOCK<='0';OE<='0'; NEXT_STATE <=ST1;
WHEN ST1=>ALE<='1';START<='1';LOCK<='0';OE<='0'; NEXT_STATE <=ST2;
WHEN ST2=>ALE<='0';START<='0';LOCK<='0';OE<='0';
IF (EOC='1') THEN NEXT_STATE<=ST3;
ELSE NEXT_STATE<=ST2;
END IF;
WHEN ST3=>ALE<='0';START<='0';LOCK<='0';OE<='1';NEXT_STATE<=ST4;
WHEN ST4=>ALE<='0';START<='0';LOCK<='0';OE<='1';NEXT_STATE<=ST0;
WHEN OTHERS=>NEXT_STATE<=ST0;
END CASE;
END PROCESS COM;
REG: PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS REG;
LATCH1:PROCESS (LOCK)
BEGIN
IF LOCK'EVENT AND LOCK='1' THEN REGL<=D;
END IF;
END PROCESS LATCH1;
END BEHAV;

Answer 2

Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
---第12行 应该改成 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
有PORT的另外半个括号

TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,);
-----第15行ST4后面的逗号去掉 ,还有程序里面有的地方是ST0 有的地方是STO,注意一下

Answer 3

Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);这一句分号之前再加个括号
TYPE STATES IS (STO,ST1,ST2,ST3,ST4,);这一行ST4后面的逗号去掉
REG PRECESS (CLK) 这一行REG后面加冒号
IF (CLK'ENENT AND CLK='1') THEN CURRENT_STATE<NEXT_STATE;ENDIF;
这一行赋值号使用错误，endif之间少个空格
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,);
-----第15行ST4后面的逗号去掉 ,还有程序里面有的地方是ST0 有的地方是STO,注意一下
这个是ADC0809的接口控制器吧，没问题，只是你太不认真了